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This 8mm Chip Packs Serious Power—and Could Revolutionize Industrial AI Design

FutureThis 8mm Chip Packs Serious Power—and Could Revolutionize Industrial AI Design
Microchip Technology
Microchip Technology

On Friday, Microchip Technology unveiled the MCP16701, a cutting-edge Power Management Integrated Circuit (PMIC) tailored for Memory Protection Unit (MPU) and Field-Programmable Gate Array (FPGA) developers.

This innovative single-chip solution incorporates eight 1.5A buck converters, four 300mA internal Low Dropouts (LDOs), and one external metal-oxide Semiconductor Field-Effect Transistor (MOSFET) driver controller.

As AI technology continues to permeate computing, data centers, and industrial applications, the industry is experiencing a surge in demand for efficient power management solutions.

The MCP16701 addresses this need by significantly reducing component count by over 60% compared to conventional discrete solutions, resulting in up to 48% space savings. Packaged in a compact 8mm × 8mm Very-thin Quad Flat No-lead Package (VQFN) format, it’s ideally suited for applications where space is at a premium, according to company representatives.

The device boasts a configurable feature set to support Microchip’s PIC64-GX MPU and PolarFire FPGA. It also incorporates an I2C communication interface, enhancing connectivity between the PMIC and other system components.

Operating across a broad temperature range from -40°C to 105°C (-40°F to 221°F), the MCP16701 ensures consistent performance in diverse environmental conditions. It offers the flexibility to adjust output voltage levels dynamically for all converters in 12.5 mV or 25 mV increments.

Rudy Jaramillo, Vice President of Microchip’s Analog Power and Interface Division, commented, “With the introduction of the MCP16701, Microchip is setting a new standard in PMIC technology by offering an unprecedented level of integration and flexibility. This advanced PMIC is designed specifically for high-performance applications, enabling our customers to streamline their design process.”

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