The Korea Ceramic Technology Institute announced Tuesday that it has developed an ultra-thin ceramic semiconductor package substrate measuring just about 0.004 inches thick.
The groundbreaking technology, developed by a research team led by Drs. Shin Hyo Soon and Ji Sang Soo, are drawing attention as an innovative solution that simultaneously meets the demands for high-speed signal processing and power efficiency in AI semiconductors.
The institute reports that the recent surge in AI semiconductor adoption has dramatically increased demand for package substrates capable of implementing high-density circuits on thin, expansive surfaces.
While traditional low-cost polymer substrates suffer from significant signal loss, interest has grown in glass substrates that can accommodate fine circuitry. However, these substrates face challenges, including the complexity of the via process and their inherent fragility. Vias are minute conduits that vertically connect silicon chips to motherboards, facilitating the passage of electrical signals.
Using a patented proprietary lamination and sintering method, the research team stacked ceramic sheets in thin layers, minimizing shrinkage at low temperatures. During the heating process, ceramic sheets typically shrink considerably. However, the team reduced the shrinkage rate from 15% to just 0.05% while achieving a thickness of about 0.008 inches.
The research team said the technology fundamentally addresses the shrinkage issue that has been a critical challenge for ceramic substrates and that it overcomes the limitations of existing ceramic substrates, which were incompatible with semiconductor processing equipment.