Samsung Electronics’ semiconductor research lab has captured industry attention by successfully implementing vertically stacked semiconductor devices at an unprecedented small size.
While the industry standard for gate pitch was previously 48 nanometers (nm), Samsung’s new implementation measures a mere 42nm. Gate pitch represents the width of a single transistor.
Not only did they minimize device size, but they also became the world’s first to create a vertical stacked three-dimensional device with a nanosheet channel (an ultra-thin film that conducts current), effectively doubling energy efficiency.
This breakthrough in vertical integration has set a new benchmark for the industry’s smallest gate pitch, overcoming horizontal integration limitations.
On Wednesday, Samsung announced their groundbreaking achievement at the Very Large Scale Integration (VLSI) symposium in the U.S. They unveiled the world’s first three-dimensional stacked field-effect transistor (3D Stacked FET) structure with a 42nm gate pitch.
Gate pitch, the distance between adjacent gate centers, is a crucial indicator of integration density. A smaller pitch allows for more transistors per unit area.
Prior to this announcement, the industry’s minimum gate pitch stood at 48nm. Samsung’s research team has now redefined this standard by reducing it to 42nm.
They’ve also achieved a world-leading three-layer (3/3) nanosheet channel, surpassing the previous 2/2 layer standard.
Vertical stacking, a concept first introduced in memory semiconductors, has now been successfully applied to logic semiconductors. Notable examples of this approach include V-NAND in NAND flash and high-bandwidth memory (HBM) in dynamic random access memory (DRAM), which overcame area limitations through stacking.
This innovation is viewed as a structural breakthrough, challenging the physical constraints of horizontal integration – the measure of how many transistors can fit in a given area.
By stacking transistors vertically, the occupied area is halved, theoretically doubling the integration density per unit area. This allows twice as many transistors to fit on a wafer of the same size.
This marks a pivotal shift from “How small can we make it?” to “How high can we stack it?”
Samsung’s semiconductor research lab has incorporated three nanosheet channels in each layer, widening the pathways for current flow. The key to this innovation lies in the successful development of an intermediate insulation layer, preventing electrical interference between upper and lower transistors.
Notably, they’ve pioneered a direct vertical connection (RBC) in an I-shape, a world first for connecting upper and lower transistors.
Unlike the previous C-shaped bypass connection (Wrap-around Contact) that utilized transistor sides, the new RBC method directly pierces through upper and lower transistors vertically in an I-shape. This process is known to be extremely challenging, requiring over three times the depth.
This innovation promises double the energy efficiency and a 100% performance boost, marking a significant leap forward for artificial intelligence (AI) and high-performance computing (HPC) chips.
The research team suggests that mass production of this structure could lead to unprecedented improvements in both energy efficiency and performance compared to current generations.
Energy efficiency correlates directly with the number of transistors in a given area. The vertical stacking structure doubles the transistor count per unit area, thus doubling energy efficiency.
Hwang Dong-hoon, a senior researcher at Samsung’s semiconductor lab, explained that traditional semiconductor processes typically see about 15% performance improvement per generation. In contrast, the vertical stacking structure can theoretically double performance due to the increased transistor count.
This technology is particularly suited for next-generation AI and HPC logic semiconductors, enabling more computations in a smaller area with lower power consumption.
The research team likened their achievement to making bricks. The next challenge is to use these bricks to construct an actual circuit – or house.
Kwon Wook-hyun, a master at Samsung’s semiconductor research lab, elaborated that this research vertically stacks the fundamental units of logic products – n-type and p-type transistors, which control current flow in opposite directions. It’s analogous to creating bricks in construction.
He added that the next step towards commercialization involves developing test circuits (Ring Oscillator) and high-speed temporary memory circuits (SRAM) to verify proper circuit operation.
