SK Hynix has unveiled next-generation technologies, including Hybrid Bonding and I-HBM, to address thermal management challenges in high-bandwidth memory (HBM). The company notably referenced Intel Corporation’s Embedded Multi-die Interconnect Bridge (EMIB) technology as an advanced packaging solution, hinting at potential collaboration with the U.S. tech giant.
HBM currently faces obstacles in stacking beyond 16 layers, with heat management becoming a critical issue as AI demand surges. Enhancing HBM is crucial for storing and processing more data faster, but this evolution leads to increased heat generation and power consumption.
Industry sources reported on Wednesday that SK Hynix presented its solutions for HBM’s technical hurdles at the Hot Chips 2026 conference at Stanford University, showcasing Hybrid Bonding and I-HBM technologies.
The company explained that signal bandwidth nearly doubles every two generations, resulting in a 2.2-fold increase in thermal stress on existing processes and packaging technologies.
HBM consists of vertically stacked dynamic random access memory (DRAM) chips. Through-silicon vias (TSVs) are electrodes formed by filling tiny holes in the center of stacked silicon chips with metals like copper. These TSVs act as conduits, enabling vertical flow of electrical signals and power.
As HBM generations advance, the number of TSVs increases with bandwidth. This expansion in TSV count leads to larger footprints, creating structural limitations that hinder heat dissipation as stacks become taller, thinner, and denser.
Ineffective heat dissipation causes chip temperatures to rise, triggering performance-reducing throttling. This can result in data errors or shortened chip lifespan. In HBM structures, heat becomes increasingly trapped in upper layers, making thermal management a significant barrier to increasing layer count.
Hybrid Bonding: Enabling Higher Stacks with Lower Thermal Resistance
Hybrid Bonding is a cutting-edge technology that directly connects chips with fine pitch. Pitch refers to the space between TSVs, with narrower pitches allowing for denser TSV packing in the same area.
Previous methods used MR-MUF, which involved melting small metal bumps between chips. Hybrid Bonding, however, directly bonds copper surfaces without bumps, enabling finer connections and improving thermal management for high-layer stacking.
SK Hynix reports that Hybrid Bonding can reduce TSV pitch from about 30 micrometers (µm) to under 18 µm, increase core die thickness by 24%, and lower thermal resistance by 35% even with more layers. The company is researching this technology for stacks exceeding 20 layers, targeting HBM5 implementation.
I-HBM: Precision Management of Internal HBM Hotspots
While Hybrid Bonding tackles thermal issues by modifying HBM’s structure, I-HBM focuses on managing specific heat concentration points within HBM. This approach differs from Samsung Electronics’ HPB (Heat Path Block) technology and Micron’s base die circuit optimization.
I-HBM incorporates special materials near D2D PHY pathways, creating dedicated heat escape routes while preventing electrical conduction. SK Hynix claims this can further reduce thermal resistance by over 30%.
SK Hynix has also unveiled its 2.5D HBM packaging technology, notably mentioning Intel Corporation’s EMIB alongside Taiwan’s TSMC’s CoWoS-L, R, and S technologies. EMIB is Intel Corporation’s advanced packaging method that uses silicon bridges to connect chips.
While TSMC has dominated the 2.5D HBM packaging market, SK Hynix’s inclusion of Intel Corporation’s EMIB as a potential next-gen HBM packaging solution suggests possible collaboration between the two companies. Canadian tech news outlet WCCFtech highlighted this development, noting speculation about a potential joint venture between Intel Corporation and SK Hynix in the memory sector.
